Address registers and address computation.pdf

💡Recall

🖋 Notes

Address registers and address computation

Address of a memory location

• number of consecutive bytes

  from the beginning of the RAM memory and the beginning of that memory location

Memory Segment (”a street”)

• uninterrupted sequence of memory locations, used for similar purposes during a program execution

<aside> 💡 both basic address and segment’s size have 32 bits value representations

</aside>

• in the family of 8086-based processors, segment has 2 meanings:
  • block of memory of discrete size, called a physical segment
  • the number of bytes in a physical memory segment is:
    • 64K for 16-bit processors
    • 4 gigabytes for 32-bit processors
  • variable-sized block of memory, called a logical segment
    • is program's code or data

Segment Selector

• a numeric value of 16 bits which selects uniquely the accessed segment and his features
• defined and provided by the operating system

Offset

• address of a location relative to the beginning of a segment
• number of bytes between the beginning of that segment and that particular memory location
• valid only if his numerical value, on 32 bits, doesn’t exceed the segment’s limit which refers to

Address Specification

• pair of a segment selector and an offset = FAR address

• if specified only by offset = NEAR address

• in hexadecimal an address specification can be written as:

  

  • in this case, the selector s3s2s1s0 shows a segment access which has the base address as b7b6b5b4b3b2b1b0 and a limit l7l6l5l4l3l2l1l0

  • the base and the limit are obtained by the processor after performing a segmentation process

  • to give access to the specific location, the following condition must be accomplished:

    

  • the segmentation address computation will be performed as:

    

    • where a7a6a5a4a3a2a1a0 is the computed address (hexadecimal form)

  • the above output address is named a linear address (or segmentation address)

Example

A concrete example of an address specification is: 8:1000h.

To compute the linear address corresponding to this specification, the processor will do the following:

1. CHECKS if the segment with the value 8 was defined by the operating system and blocks the access, such a segment wasn’t defined (memory violation error…)
2. EXTRACTS the base address (B) and the segment’s limit (L)
   • for example, as a result we may have B – 2000h and L = 4000h
3. VERIFIES if the offset exceeds the segment’s limit: 1000h > 4000h, if so ⇒ access would be blocked
4. ADDS the offset to B and obtains the linear address 3000h (1000h + 2000h)
   • this computation is performed by the ADR component from BIU

This kind of addressing is called segmentation and we are talking about the segmented addressing model.

Segments

The x86 architecture allows 4 types of segments:

• code segment
  • contains instructions
• data segment
  • containS data which instructions work on
• stack segment
• extra segment
  • supplementary data segment
• every program is composed by one or more segments of one or more of the above specified types
• at any given moment during run time there is only at most one active segment of any type
• CS (Code Segment), DS (Data Segment), SS (Stack Segment) and ES (Extra Segment) from BIU
  • on 32 bits
    • determine
      • the starting addresses and the dimensions of the 4(currently) active segments: code, data, stack and extra segments
  • on 16 bits
    • contain
      • the starting addresses and the dimensions of the 4(currently) active segments: code, data, stack and extra segments
• registers FS and GS
  • store selectors pointing to other auxiliary segments without having predetermined meaning
• CS, DS, SS ES, FS and GS are called segment registers (or selector registers)
• register EIP
  • offers also the possibility of accessing its less significant word by referring to the IP subregister
  • contains the offset of the current instruction inside the current code segment, this register being managed exclusively by BIU